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Quad-Channel Digital Isolators ADuM1410/ADuM1411/ADuM1412
FEATURES
Low power operation 5 V operation 1.3 mA per channel maximum @ 0 Mbps to 2 Mbps 4.0 mA per channel maximum @ 10 Mbps 3 V operation 0.8 mA per channel maximum @ 0 Mbps to 2 Mbps 1.8 mA per channel maximum @ 10 Mbps Bidirectional communication 3 V/5 V level translation High temperature operation: 105C Up to 10 Mbps data rate (NRZ) Programmable default output state High common-mode transient immunity: >25 kV/s 16-lead, RoHS-compliant, SOIC wide body package Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL 1577 CSA component acceptance notice #5A VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 560 V peak
FUNCTIONAL BLOCK DIAGRAMS
VDD1 1 GND1 2 VIA 3 VIB 4 VIC 5 VID 6 DISABLE 7 GND1 8
ADuM1410
ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE
16 15 14 13 12 11 10 9
VDD2 GND2 VOA VOB VOC VOD
06580-001
CTRL2 GND2
Figure 1. ADuM1410
VDD1 1 GND1 2 VIA 3 VIB 4 VIC 5 VOD 6 CTRL1 7 GND1 8
16 15
ADuM1411
ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE
VDD2 GND2 VOA VOB VOC VID
06580-002 06580-003
14 13 12 11 10 9
CTRL2 GND2
Figure 2. ADuM1411
VDD1 1 GND1 2 VIA 3 VIB 4 VOC 5 VOD 6 CTRL1 7 GND1 8
16 15
APPLICATIONS
General-purpose multichannel isolation SPI interface/data converter isolation RS-232/RS-422/RS-485 transceivers Industrial field bus isolation
ADuM1412
ENCODE ENCODE DECODE DECODE DECODE DECODE ENCODE ENCODE
VDD2 GND2 VOA VOB VIC VID CTRL2 GND2
14 13 12 11 10 9
Figure 3. ADuM1412
GENERAL DESCRIPTION
The ADuM141x are four-channel digital isolators based on Analog Devices, Inc. iCoupler(R) technology. Combining high speed CMOS and monolithic air core transformer technologies, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices. By avoiding the use of LEDs and photodiodes, iCoupler devices remove the design difficulties commonly associated with optocouplers. The usual concerns that arise with optocouplers, such as uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects, are eliminated with the simple iCoupler digital interfaces and stable performance characteristics. The need for external drivers and other discrete components is eliminated with these iCoupler products.
1
1
Furthermore, iCoupler devices consume one-tenth to one-sixth the power of optocouplers at comparable signal data rates. The ADuM141x isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide) up to 10 Mbps. All models operate with the supply voltage on either side ranging from 2.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier. All products also have a default output control pin. This allows the user to define the logic state the outputs are to adopt in the absence of the input power. Unlike other optocoupler alternatives, the ADuM141x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and during power-up/power-down conditions.
Protected by U.S. Patents 5,952,849, 6,873,065 and 7,075,329. Other patents pending. Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
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ADuM1410/ADuM1411/ADuM1412 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics--5 V Operation................................ 3 Electrical Characteristics--3 V Operation................................ 5 Electrical Characteristics--Mixed 5 V/3 V or 3 V/5 V Operation....................................................................................... 7 Package Characteristics ............................................................. 10 Regulatory Information............................................................. 10 Insulation and Safety-Related Specifications.......................... 10 DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Insulation Characteristics.......................................................... 11 Recommended Operating Conditions .................................... 11 Absolute Maximum Ratings ......................................................... 12 ESD Caution................................................................................ 12 Pin Configurations and Function Descriptions ......................... 13 Typical Performance Characteristics ........................................... 17 Applications Information .............................................................. 19 PC Board Layout ........................................................................ 19 Propagation Delay-Related Parameters................................... 19 DC Correctness and Magnetic Field Immunity........................... 19 Power Consumption .................................................................. 20 Insulation Lifetime ..................................................................... 20 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22
REVISION HISTORY
6/07--Rev. F to Rev. G Updated VDE Certification Throughout ...................................... 1 Changes to Features and Applications........................................... 1 Changes to DC Specifications in Table 1....................................... 3 Changes to DC Specifications in Table 2....................................... 5 Changes to DC Specifications in Table 3....................................... 7 Changes to Regulatory Information Section .............................. 10 Added Table 10 ............................................................................... 12 Added Insulation Lifetime Section .............................................. 21 2/07--Rev. E to Rev F Added ADUM1410ARWZ ................................................Universal Updated Pin Name CTRL to CTRL2 Throughout........................ 1 Changes to Ordering Guide .......................................................... 21 10/06--Rev. D to Rev. E Added ADuM1411 and ADuM1412 ...............................Universal Deleted ADuM1310 ...........................................................Universal Changes to Features ..........................................................................1 Changes to Specifications Section...................................................3 Updated Outline Dimensions....................................................... 20 Changes to Ordering Guide .......................................................... 20 3/06--Rev. C to Rev. D Added Note 1 and Changes to Figure 2..........................................1 Changes to Absolute Maximum Ratings..................................... 11 11/05--Rev. SpB to Rev. C: Initial Version
Rev. G | Page 2 of 24
ADuM1410/ADuM1411/ADuM1412 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--5 V OPERATION
4.5 V VDD1 5.5 V, 4.5 V VDD2 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective ground. Table 1.
Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM1410, Total Supply Current, Four Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 or VDD2 Supply Current All Models Input Currents Symbol IDDI (Q) IDDO (Q) Min Typ 0.50 0.38 Max 0.73 0.53 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q) IDD1 (10) IDD2 (10)
2.4 1.2 8.8 2.8
3.2 1.6 12 4.0
mA mA mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q) IDD2 (Q)
2.2 1.8
2.8 2.4
mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (10) IDD2 (10)
5.4 3.8
7.6 5.3
mA mA
IDD1 (Q), IDD2 (Q)
2.0
2.6
mA
DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 0 V VIA, VIB, VIC, VID VDD1 or VDD2, 0 V VCTRL1, VCTRL2 VDD1 or VDD2, 0 V VDISABLE VDD1
IDD1 (10), IDD2 (10) IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE VIH VIL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL -10
4.6 +0.0 1
6.5 +10
mA A
Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages
2.0 0.8 (VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.4 5.0 4.8 0.0 0.04 0.2
0.1 0.1 0.4
V V V V V V V
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM141xARWZ Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4
PW tPHL, tPLH PWD 1 20 65
1000 100 40
ns Mbps ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
Rev. G | Page 3 of 24
ADuM1410/ADuM1411/ADuM1412
Parameter Propagation Delay Skew 5 Channel-to-Channel Matching 6 ADuM141xBRWZ Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 All Models Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Enable Time 8 Input Disable Time8 Input Dynamic Supply Current per Channel 9 Output Dynamic Supply Current per Channel9
1
Symbol tPSK tPSKCD/OD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD
Min
Typ
Max 50 50 100
Unit ns ns ns Mbps ns ns ps/C ns ns ns
Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
10 20
30 5
50 5 30 5 6
tR/tF |CMH|
25
2.5 35
ns kV/s
CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
|CML|
25
35
kV/s
fr tENABLE tDISABLE IDDI (D) IDDO (D)
1.2 2.0 5.0 0.12 0.04
Mbps s s mA/ Mbps mA/ Mbps
VIA, VIB, VIC, VID = 0 V or VDD1 VIA, VIB, VIC, VID = 0 V or VDD1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. G | Page 4 of 24
ADuM1410/ADuM1411/ADuM1412
ELECTRICAL CHARACTERISTICS--3 V OPERATION
2.7 V VDD1 3.6 V, 2.7 V VDD2 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C, VDD1 = VDD2 = 3.0 V. All voltages are relative to their respective ground. Table 2.
Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent Output Supply Current per Channel, Quiescent ADuM1410, Total Supply Current, Four Channels 1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 Supply Current VDD2 Supply Current ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 or VDD2 Supply Current 10 Mbps (BRWZ Version Only) VDD1 or VDD2 Supply Current All Models Input Currents Symbol IDDI (Q) IDDO (Q) Min Typ 0.25 0.19 Max 0.38 0.33 Unit mA mA Test Conditions
IDD1 (Q) IDD2 (Q)
1.2 0.8
1.6 1.0
mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (10) IDD2 (10)
4.5 1.4
6.5 1.8
mA mA
IDD1 (Q) IDD2 (Q)
1.0 0.9
1.9 1.7
mA mA
DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (10) IDD2 (10)
3.1 2.1
4.5 3.0
mA mA
IDD1 (Q), IDD2 (Q)
1.0
1.8
mA
DC to 1 MHz logic signal frequency 5 MHz logic signal frequency 0 V VIA, VIB, VIC, VID VDD1 or VDD2, 0 V VCTRL1, VCTRL2 VDD1 or VDD2, 0 V VDISABLE VDD1
IDD1 (10), IDD2 (10) IIA, IIB, IIC, IID, ICTRL1, ICTRL2, IDISABLE VIH VIL VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL -10
2.6
3.8
mA A
+0.01 +10
Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages
1.6 0.4 (VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.4 3.0 2.8 0.0 0.04 0.2
0.1 0.1 0.4
V V V V V V V
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM141xARWZ Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Propagation Delay Skew 5
PW tPHL, tPLH PWD tPSK 1 20 75
1000 100 40 50
ns Mbps ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
Rev. G | Page 5 of 24
ADuM1410/ADuM1411/ADuM1412
Parameter Channel-to-Channel Matching 6 ADuM141xBRWZ Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6 All Models Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate Input Enable Time 8 Input Disable Time8 Input Dynamic Supply Current per Channel 9 Output Dynamic Supply Current per Channel9
1
Symbol tPSKCD/OD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD
Min
Typ
Max 50 100
Unit ns ns Mbps ns ns ps/C ns ns ns
Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
10 20
40 5
60 5 30 5 6
tR/tF |CMH| |CML| fr tENABLE tDISABLE IDDI (D) IDDO (D)
25 25
2.5 35 35 1.1 2.0 5.0 0.07 0.02
ns kV/s kV/s Mbps s s mA/ Mbps mA/ Mbps
CL = 15 pF, CMOS signal levels VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V VIA, VIB, VIC, VID = 0 V or VDD1 VIA, VIB, VIC, VID = 0 V or VDD1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. G | Page 6 of 24
ADuM1410/ADuM1411/ADuM1412
ELECTRICAL CHARACTERISTICS--MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation: 4.5 V VDD1 5.5 V, 2.7 V VDD2 3.6 V; 3 V/5 V operation: 2.7 V VDD1 3.6 V, 4.5 V VDD2 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at TA = 25C; VDD1 = 3.0 V, VDD2 = 5 V; or VDD1 = 5 V, VDD2 = 3.0 V. All voltages are relative to their respective ground. Table 3.
Parameter DC SPECIFICATIONS Input Supply Current per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current per Channel, Quiescent 5 V/3 V Operation 3 V/5 V Operation ADuM1410, Total Supply Current, Four Channels 1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRWZ Version Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation ADuM1411, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRWZ Version Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation IDD2 (Q) 0.9 1.7 1.7 2.4 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency IDD2 (Q) 0.8 1.2 1.0 1.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency Symbol IDDI (Q) 0.50 0.25 IDDO (Q) 0.19 0.38 0.33 0.53 mA mA 0.73 0.38 mA mA Min Typ Max Unit Test Conditions
IDD1 (Q) 2.4 1.2 3.2 1.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
IDD1 (10) 8.6 3.4 IDD2 (10) 1.4 2.6 1.8 3.0 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency 11 6.5 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency
IDD1 (Q) 2.2 1.0 2.8 1.9 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
IDD1 (10) 5.4 3.1 IDD2 (10) 2.1
Rev. G | Page 7 of 24
7.6 4.5 3.0
mA mA mA
5 MHz logic signal frequency 5 MHz logic signal frequency 5 MHz logic signal frequency
ADuM1410/ADuM1411/ADuM1412
Parameter 3 V/5 V Operation ADuM1412, Total Supply Current, Four Channels1 DC to 2 Mbps VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation 10 Mbps (BRWZ Version Only) VDD1 Supply Current 5 V/3 V Operation 3 V/5 V Operation VDD2 Supply Current 5 V/3 V Operation 3 V/5 V Operation All Models Input Currents IDD2 (Q) 1.0 2.0 1.8 2.6 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency Symbol Min Typ 3.8 Max Unit 5.3 mA Test Conditions 5 MHz logic signal frequency
IDD1 (Q) 2.0 1.0 2.6 1.8 mA mA DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency
IDD1 (10) 4.6 2.6 IDD2 (10) 2.6 4.6 IIA, IIB, IIC, IID, -10 ICTRL1, ICTRL2, IDISABLE VIH 2.0 1.6 VIL +0.01 3.8 6.5 +10 mA mA A 5 MHz logic signal frequency 5 MHz logic signal frequency 0 V VIA,VIB, VIC,VID VDD1 or VDD2, 0 V VCTRL1,VCTRL2 VDD1 or VDD2, 0 V VDISABLE VDD1 6.5 3.8 mA mA 5 MHz logic signal frequency 5 MHz logic signal frequency
Logic High Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic Low Input Threshold 5 V/3 V Operation 3 V/5 V Operation Logic High Output Voltages Logic Low Output Voltages
V V 0.8 0.4 V V V V V V V
VOAH, VOBH, VOCH, VODH VOAL, VOBL, VOCL, VODL
(VDD1 or VDD2) - 0.1 (VDD1 or VDD2) - 0.4
(VDD1 or VDD2) (VDD1 or VDD2) - 0.2 0.0 0.04 0.2
0.1 0.1 0.4
IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 400 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
SWITCHING SPECIFICATIONS ADuM141xARWZ Minimum Pulse Width 2 Maximum Data Rate 3 Propagation Delay 4 Pulse Width Distortion, |tPLH - tPHL|4 Propagation Delay Skew 5 Channel-to-Channel Matching 6 ADuM141xBRWZ Minimum Pulse Width2 Maximum Data Rate3 Propagation Delay4 Pulse Width Distortion, |tPLH - tPHL|4 Change vs. Temperature Propagation Delay Skew5 Channel-to-Channel Matching, Codirectional Channels6 Channel-to-Channel Matching, Opposing-Directional Channels6
PW tPHL, tPLH PWD tPSK tPSKCD/OD PW tPHL, tPLH PWD tPSK tPSKCD tPSKOD
Rev. G | Page 8 of 24
1 25
70
1000 ns Mbps 100 ns 40 ns 50 ns 50 ns 100 ns Mbps ns ns ps/C ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
10 25
35 5
60 5 30 5 6
ADuM1410/ADuM1411/ADuM1412
Parameter All Models Output Rise/Fall Time (10% to 90%) 5 V/3 V Operation 3 V/5 V Operation Common-Mode Transient Immunity at Logic High Output 7 Common-Mode Transient Immunity at Logic Low Output7 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Enable Time 8 Input Disable Time8 Input Dynamic Supply Current per Channel 9 5 V Operation 3 V Operation Output Dynamic Supply Current per Channel9 5 V Operation 3 V Operation
1
Symbol tR/tF
Min
Typ
Max Unit
Test Conditions CL = 15 pF, CMOS signal levels
|CMH| |CML| fr
25 25
2.5 2.5 35 35
ns ns kV/s kV/s
VIx = VDD1 or VDD2, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, VCM = 1000 V, transient magnitude = 800 V
tENABLE tDISABLE IDDI (D)
1.2 1.1 2.0 5.0
Mbps Mbps s s
VIA, VIB, VIC, VID = 0 V or VDD1 VIA, VIB, VIC, VID = 0 V or VDD1
0.12 0.07 IDDO (D) 0.04 0.02
mA/ Mbps mA/ Mbps
mA/ Mbps mA/ Mbps
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 through Figure 10 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 11 through Figure 15 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1410/ADuM1411/ADuM1412 channel configurations. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. 5 tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 |CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. |CML| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient magnitude is the range over which the common mode is slewed. 8 Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the much shorter duration as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 14). 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 8 through Figure 10 for information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current for a given data rate.
Rev. G | Page 9 of 24
ADuM1410/ADuM1411/ADuM1412
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction-to-Case Thermal Resistance Side 1 Side 2
1 2
Symbol RI-O CI-O CI JCI JCO
Min
Typ 1012 2.2 4.0 33 28
Max
Unit pF pF C/W C/W
Test Conditions f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM141x have been approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels. Table 5.
UL Recognized Under 1577 Component Recognition Program 1 Double/Reinforced Insulation, 2500 V rms Isolation Voltage CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms (1131 V peak) maximum working voltage Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 Reinforced insulation, 560 V peak
File E214100
1 2
File 2471900-4880-0001
In accordance with UL1577, each ADuM141x is proof tested by applying an insulation test voltage 3000 V rms for 1 sec (current leakage detection limit = 5 A). In accordance with DIN V VDE V 0884-10, each ADuM141x is proof tested by applying an insulation test voltage 1050 V peak for 1 second (partial discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 2500 7.7 8.1 0.017 >175 IIIa Unit V rms mm min mm min mm min V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. G | Page 10 of 24
ADuM1410/ADuM1411/ADuM1412
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval. Table 7.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS
350
Conditions
Symbol
Characteristic I to IV I to III I to II 40/105/21 2 560 1050
Unit
VIORM x 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM x 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM x 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure; see Figure 4
VIORM VPR VPR
V peak V peak
896 672 VTR 4000
V peak V peak V peak
VIO = 500 V
TS IS1 IS2 RS
150 265 335 >109
C mA mA
RECOMMENDED OPERATING CONDITIONS
Table 8.
Parameter Operating Temperature Supply Voltages 1 Input Signal Rise and Fall Times
1
300
SAFETY-LIMITING CURRENT (mA)
250
SIDE #2
200
Symbol TA VDD1, VDD2
Min -40 2.7
Max +105 5.5 1.0
Unit C V ms
150
SIDE #1
100 50 0 0 50 100 150 CASE TEMPERATURE (C) 200
All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields.
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN V VDE V 0884-10
06580-007
Rev. G | Page 11 of 24
ADuM1410/ADuM1411/ADuM1412 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 9.
Parameter Storage Temperature (TST) Range Ambient Operating Temperature (TA) Range Supply Voltages (VDD1, VDD2)1 Input Voltages (VIA, VIB, VIC, VID, VCTRL1, VCTRL2, VDISABLE)1, 2 Output Voltages (VOA, VOB, VOC, VOD)1, 2 Average Output Current per Pin3 Side 1 (IO1) Side 2 (IO2) Common-Mode Transients4
1 2
Rating -65C to +150C -40C to +105C -0.5 V to +7.0 V -0.5 V to VDDI + 0.5 V -0.5 V to VDDO + 0.5 V -18 mA to +18 mA -22 mA to +22 mA -100 kV/s to +100 kV/s
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section. 3 See Figure 4 for maximum rated current values for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.
Table 10. Maximum Continuous Working Voltage 1
Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation
1
Max 565 1131 560 1131 560
Unit V peak V peak V peak V peak V peak
Constraint 50-year minimum lifetime Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. G | Page 12 of 24
ADuM1410/ADuM1411/ADuM1412 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1 GND1* 2 VIA 3 VIB 4 VIC 5 VID 6 DISABLE 7 GND1* 8
16 VDD2 15 GND2*
ADuM1410
TOP VIEW (Not to Scale)
14 VOA 13 VOB 12 VOC 11 VOD 10 CTRL2 9
GND2*
06580-004
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 5. ADuM1410 Pin Configuration
Table 11. ADuM1410 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 Mnemonic VDD1 GND1 VIA VIB VIC VID DISABLE GND1 GND2 CTRL2 Description Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state determined by CTRL2. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, VOC, and VOD outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, VOC, and VOD outputs are low when CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
11 12 13 14 15 16
VOD VOC VOB VOA GND2 VDD2
Rev. G | Page 13 of 24
ADuM1410/ADuM1411/ADuM1412
VDD1 1 GND1* 2 VIA 3 VIB 4 VIC 5 VOD 6 CTRL1 7 GND1* 8
16 15
VDD2 GND2* VOA VOB VOC VID CTRL2 GND2*
06580-005
ADuM1411
TOP VIEW (Not to Scale)
14 13 12 11 10 9
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 6. ADuM1411 Pin Configuration
Table 12. ADuM1411 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VIC VOD CTRL1 Description Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Default Output Control. Controls the logic state the outputs assume when the input power is off. VOD output is high when CTRL1 is high or disconnected and VDD2 is off. VOD output is low when CTRL1 is low and VDD2 is off. When VDD2 power is on, this pin has no effect. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA, VOB, and VOC outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, and VOC outputs are low when CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect. Logic Input D. Logic Output C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
8 9 10
GND1 GND2 CTRL2
11 12 13 14 15 16
VID VOC VOB VOA GND2 VDD2
Rev. G | Page 14 of 24
ADuM1410/ADuM1411/ADuM1412
VDD1 1 GND1* 2 VIA 3 VIB 4 VOC 5 VOD 6 CTRL1 7 GND1* 8
16 15
VDD2 GND2* VOA VOB VIC VID CTRL2 GND2*
06580-006
ADuM1412
TOP VIEW (Not to Scale)
14 13 12 11 10 9
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 7. ADuM1412 Pin Configuration
Table 13. ADuM1412 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 Mnemonic VDD1 GND1 VIA VIB VOC VOD CTRL1 Description Supply Voltage for Isolator Side 1 (2.7 V to 5.5 V). Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Default Output Control. Controls the logic state the outputs assume when the input power is off. VOC and VOD outputs are high when CTRL1 is high or disconnected and VDD2 is off. VOC and VOD outputs are low when CTRL1 is low and VDD2 is off. When VDD2 power is on, this pin has no effect. Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is recommended. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Default Output Control. Controls the logic state the outputs assume when the input power is off. VOA and VOB outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA and VOB outputs are low when CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect. Logic Input D. Logic Input C. Logic Output B. Logic Output A. Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is recommended. Supply Voltage for Isolator Side 2 (2.7 V to 5.5 V).
8 9 10
GND1 GND2 CTRL2
11 12 13 14 15 16
VID VIC VOB VOA GND2 VDD2
Rev. G | Page 15 of 24
ADuM1410/ADuM1411/ADuM1412
Table 14. Truth Table (Positive Logic)
VIx Input 1 H L X X X CTRLX Input 2 X X H or NC L H or NC VDISABLE State 3 L or NC L or NC H H X VDDI State 4 Powered Powered X X Unpowered VDDO State 5 Powered Powered Powered Powered Powered VOx Output1 H L H L H Description Normal operation, data is high. Normal operation, data is low. Inputs disabled. Outputs are in the default state as determined by CTRLX. Inputs disabled. Outputs are in the default state as determined by CTRLX. Input unpowered. Outputs are in the default state as determined by CTRLX. Outputs return to input state within 1 s of VDDI power restoration. See the pin function descriptions (Table 11, Table 12, and Table 13) for more details. Input unpowered. Outputs are in the default state as determined by CTRLX. Outputs return to input state within 1 s of VDDI power restoration. See the pin function descriptions (Table 11, Table 12, and Table 13) for more details. Output unpowered. Output pins are in high impedance state. Outputs return to input state within 1 s of VDDO power restoration. See the pin function descriptions (Table 11, Table 12, and Table 13) for more details.
X
L
X
Unpowered
Powered
L
X
X
X
Powered
Unpowered
Z
1 2
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). CTRLX refers to the default output control signal on the input side of a given channel (A, B, C, or D). 3 Available only on ADuM1410. 4 VDDI refers to the power supply on the input side of a given channel (A, B, C, or D). 5 VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
Rev. G | Page 16 of 24
ADuM1410/ADuM1411/ADuM1412 TYPICAL PERFORMANCE CHARACTERISTICS
2.0 10 8
CURRENT/CHANNEL (mA)
1.5
CURRENT (mA)
6
5V 1.0
4
5V
3V 0.5
2 3V
06580-008
0
2
4 6 DATA RATE (Mbps)
8
10
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 8. Typical Supply Current per Input Channel vs. Data Rate for 5 V and 3 V Operation
1.0 0.9 0.8
CURRENT/CHANNEL (mA)
Figure 11. Typical ADuM1410 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
10
8
0.7 0.6 0.5 0.4 0.3 0.2 0.1
06580-009
CURRENT (mA)
5V
6
4
3V
5V 2 3V
0
2
4 6 DATA RATE (Mbps)
8
10
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 9. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (No Output Load)
1.4 1.2
Figure 12. Typical ADuM1410 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
10
8 CURRENT/CHANNEL (mA) 1.0 CURRENT (mA) 0.8 5V 0.6 0.4 3V 0.2 0 0 2 4 6 DATA RATE (Mbps) 8 10 0 0 2 4 6 DATA RATE (Mbps) 8 10 2 3V 6
4 5V
06580-010
Figure 10. Typical Supply Current per Output Channel vs. Data Rate for 5 V and 3 V Operation (15 pF Output Load)
Figure 13. Typical ADuM1411 VDD1 Supply Current vs. Data Rate for 5 V and 3 V Operation
Rev. G | Page 17 of 24
06580-013
06580-012
0
0
06580-011
0
0
ADuM1410/ADuM1411/ADuM1412
10 10
8
8
CURRENT (mA)
6
CURRENT (mA)
6
4 5V 2 3V
4 5V 2 3V
06580-014
0
2
4 6 DATA RATE (Mbps)
8
10
0
2
4 6 DATA RATE (Mbps)
8
10
Figure 14. Typical ADuM1411 VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Figure 15. Typical ADuM1412 VDD1 or VDD2 Supply Current vs. Data Rate for 5 V and 3 V Operation
Rev. G | Page 18 of 24
06580-015
0
0
ADuM1410/ADuM1411/ADuM1412 APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM141x digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is strongly recommended at the input and output supply pins (see Figure 16). Bypass capacitors are most conveniently connected between Pin 1 and Pin 2 for VDD1, and between Pin 15 and Pin 16 for VDD2. The capacitor value should be between 0.01 F and 0.1 F. The total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both ground pins on each package are connected together close to the package.
VDD1 GND1 VIA VIB VIC VID DISABLE GND1 VDD2 GND2 VOA VOB VOC VOD CTRL2 GND2
Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM141x component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM141x components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder using the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 s, a periodic set of refresh pulses indicative of the correct input state is sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 14) by the watchdog timer circuit. The magnetic field immunity of the ADuM141x is determined by the changing magnetic field, which induces a voltage in the transformer's receiving coil large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM141x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d / dt) rn2; n = 1, 2, ... , N where: is magnetic flux density (gauss). rn is the radius of the nth turn in the receiving coil (cm). N is the number of turns in the receiving coil. Given the geometry of the receiving coil in the ADuM141x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field at a given frequency can be calculated. The result is shown in Figure 18.
ADuM1410
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is important to minimize board coupling across the isolation barrier. Furthermore, users should design the board layout so that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may differ from the propagation delay time of a low-to-high transition.
INPUT (VIx) 50%
tPLH
OUTPUT (VOx)
tPHL
50%
06580-017
Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between these two propagation delay values and an indication of how accurately the timing of the input signal is preserved.
06580-016
Rev. G | Page 19 of 24
ADuM1410/ADuM1411/ADuM1412
100
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
10
POWER CONSUMPTION
The supply current at a given channel of the ADuM141x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) x (2f - fr) + IDDI (Q)
06580-018
1
0.1
0.01
f 0.5 fr f > 0.5 fr
0.001 1k
10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
For each output channel, the supply current is given by IDDO = IDDO (Q)
-3
Figure 18. Maximum Allowable External Magnetic Flux Density
f 0.5 fr
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurred during a transmitted pulse (and had the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM141x transformers. Figure 19 shows these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM141x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted previously, a 0.5 kA current would have to be placed 5 mm away from the ADuM141x to affect the operation of the component.
1000 MAXIMUM ALLOWABLE CURRENT (kA) DISTANCE = 1m 100
IDDO = (IDDO (D) + (0.5 x 10 ) x CL x VDDO) x (2f - fr) + IDDO (Q) f > 0.5 fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half the input data rate, expressed in units of Mbps. fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA). To calculate the total VDD1 and VDD2 supply current, the supply currents for each input and output channel corresponding to VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9 show per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 shows the per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 show the total VDD1 and VDD2 supply current as a function of data rate for ADuM1410/ ADuM1411/ADuM1412 channel configurations.
INSULATION LIFETIME
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM141x.
1M 10M 100M
1k
10k
100k
MAGNETIC FIELD FREQUENCY (Hz)
Figure 19. Maximum Allowable Current for Various Current-to-ADuM141x Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces can induce error voltages sufficiently large enough to trigger the
Rev. G | Page 20 of 24
06580-019
0.01
Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 10 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum CSA/VDE approved working voltages. In many cases, the
ADuM1410/ADuM1411/ADuM1412
approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM141x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the Analog Devices recommended maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 10 can be applied while maintaining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 21 or Figure 22 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 10. Note that the voltage presented in Figure 21 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE 0V
06580-020
Figure 20. Bipolar AC Waveform
RATED PEAK VOLTAGE
06580-021
0V
Figure 21. Unipolar AC Waveform
RATED PEAK VOLTAGE
06580-022
0V
Figure 22. DC Waveform
Rev. G | Page 21 of 24
ADuM1410/ADuM1411/ADuM1412 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16 9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
8 0 0.33 (0.0130) 0.20 (0.0079)
45
SEATING PLANE
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 23. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADUM1410ARWZ 1 ADUM1410ARWZ-RL1 ADuM1410BRWZ1 ADuM1410BRWZ-RL1 ADuM1411ARWZ1 ADuM1411ARWZ-RL1 ADuM1411BRWZ1 ADuM1411BRWZ-RL1 ADuM1412ARWZ1 ADuM1412ARWZ-RL1 ADuM1412BRWZ1 ADuM1412BRWZ-RL1
1
Number of Inputs, VDD1 Side 4 4 4 4 3 3 3 3 2 2 2 2
Number of Inputs, VDD2 Side 0 0 0 0 1 1 1 1 2 2 2 2
Maximum Data Rate 1 Mbps 1 Mbps 10 Mbps 10 Mbps 1 Mbps 1 Mbps 10 Mbps 10 Mbps 1 Mbps 1 Mbps 10 Mbps 10 Mbps
Maximum Propagation Delay, 5 V 100 ns 100 ns 50 ns 50 ns 100 ns 100 ns 50 ns 50 ns 100 ns 100 ns 50 ns 50 ns
Maximum Pulse Width Distortion 40 ns 40 ns 5 ns 5 ns 40 ns 40 ns 5 ns 5 ns 40 ns 40 ns 5 ns 5 ns
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
032707-B
Package Description 16-Lead SOIC_W 16-Lead SOIC_W, 13" Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Reel 16-Lead SOIC_W 16-Lead SOIC_W, 13" Reel
Package Option RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16 RW-16
Z = RoHS Compliant Part.
Rev. G | Page 22 of 24
ADuM1410/ADuM1411/ADuM1412 NOTES
Rev. G | Page 23 of 24
ADuM1410/ADuM1411/ADuM1412 NOTES
(c)2004-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06580-0-6/07(G)
Rev. G | Page 24 of 24

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